Asynchronous processing logic may provide a desirable alternative to using synchronous processing logic in signal processing or other applications. Synchronizing a plurality of synchronous processing logic devices may depend on routing clock signals and on providing a network of clock buffers to propagate synchronized clock signals to each of the synchronous logic processing devices. By contrast, asynchronous processing logic provides results that are stored whenever an operation is complete. A disadvantage of asynchronous processing logic is that the time at which output is available may depend on the complexity of a particular operation, an amount of power provided to the asynchronous processing logic, an operating temperature of the asynchronous processing logic, process variations that may have affected the operation of a particular chip or wafer, and other factors.
When using asynchronous processing logic in portable devices or other situations, minimizing power consumption involves balancing competing interests. The asynchronous processing logic may be expected to operate at a particular speed to achieve a desired throughput. At the same time, it may be desirable to operate the asynchronous processing logic at a lowest workable power level. As previously mentioned, operating temperature, process variations in manufacture, etc., may make it difficult to predict what power level will result in the desired throughput. To ensure the desired throughput, design timing margins being added which may result in higher static power consumption and higher dynamic power consumption. There is therefore a need to adjust the voltage supplied to asynchronous processing logic to maintain a desired processing throughput while minimizing power consumption.